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Signal processing and generating circuits using otra as a building block (Record no. 882772)

MARC details
000 -LEADER
fixed length control field	00848nam a2200253Ia 4500
003 - CONTROL NUMBER IDENTIFIER
control field	OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field	20220930091842.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field	220926b \|\|\|\|\|\|\|\| \|\|\|\| 00\| 0 eng d
037 ## - SOURCE OF ACQUISITION
Terms of availability	Theses
040 ## - CATALOGING SOURCE
Original cataloging agency	CRL
Transcribing agency	CRL
Language of cataloging	eng
041 ## - LANGUAGE CODE
Source of code	eng
Language code of text/sound track or separate title	eng
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name	Pandey Rajeshwari
9 (RLIN)	546926
110 ## - MAIN ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element	University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering
245 #0 - TITLE STATEMENT
Title	Signal processing and generating circuits using otra as a building block
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc.	2013
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element	TECHNOLOGY
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name	Pandey Neeta Gu.
9 (RLIN)	546927
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name	University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type	Dissertations
Source of classification or shelving scheme	Colon Classification (CC)

Holdings
Withdrawn status	Lost status	Damaged status	Not for loan	Home library	Current library	Date acquired	Total Checkouts	Barcode	Date last seen	Price effective from	Koha item type
				Central Library	Central Library	2022-09-30		TH0020134	2022-09-30	2022-09-30	Thesis