<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[Delhi University Library System Search for 'su:{ Verilog}']]> </title> <!-- prettier-ignore-start --> <link> /cgi-bin/koha/opac-search.pl?idx=&#38;q=su%3A%7B%20Verilog%7D&#38;sort_by=title_asc&#38;format=rss </link> <!-- prettier-ignore-end --> <atom:link rel="self" type="application/rss+xml" href="/cgi-bin/koha/opac-search.pl?idx=&#38;q=su%3A%7B%20Verilog%7D&#38;sort_by=title_asc&#38;format=rss" /> <description> <![CDATA[ Search results for 'su:{ Verilog}' at Delhi University Library System]]> </description> <opensearch:totalResults>22</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="/cgi-bin/koha/opac-search.pl?idx=&#38;q=su%3A%7B%20Verilog%7D&#38;sort_by=title_asc&#38;format=opensearchdescription" /> <opensearch:Query role="request" searchTerms="idx%3D%26q%3Dsu%253A%257B%2520Verilog%257D" startPage="" /> <item> <title> Advanced Digital Design with the Verilog HDL, 2 ed. </title> <dc:identifier>ISBN:9789353062767</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1671637</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/9353062764.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Michael D. Ciletti.<br /> Pearson Pearson 2017 9789353062767 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1671637">Place hold on <em>Advanced Digital Design with the Verilog HDL, 2 ed.</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1671637</guid> </item> <item> <title> Architectures for Computer Vision: From Algorithm to Chip with Verilog </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1719949</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Jeong.<br /> IEEE </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1719949">Place hold on <em>Architectures for Computer Vision: From Algorithm to Chip with Verilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1719949</guid> </item> <item> <title> Computer arithmetic and verilog HDL fundamentals </title> <dc:identifier>ISBN:9781439811245 (hbd)</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=28916</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1439811245.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Cavanagh Joseph.<br /> Boca Raton CRC Pres 2010 .<br /> xx, 951p. , Appendices A-D, 801-942p.; Index 943-951p. cm..<br /> 9781439811245 (hbd) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=28916">Place hold on <em>Computer arithmetic and verilog HDL fundamentals</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=28916</guid> </item> <item> <title> Computer Arithmetic and Verilog HDL Fundamentals </title> <dc:identifier>ISBN:9781315218229</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1768471</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1315218224.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Joseph Cavanagh.<br /> Taylor and Francis 2010 9781315218229 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1768471">Place hold on <em>Computer Arithmetic and Verilog HDL Fundamentals</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1768471</guid> </item> <item> <title> Design through Verilog HDL </title> <dc:identifier>ISBN:9789390466443</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1554247</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/939046644X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Padmanabhan.<br /> Wiley 2020 9789390466443 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1554247">Place hold on <em>Design through Verilog HDL</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1554247</guid> </item> <item> <title> Design Through Verilog HDL </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1718297</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Padmanabhan.<br /> IEEE 2004 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1718297">Place hold on <em>Design Through Verilog HDL</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1718297</guid> </item> <item> <title> Digital Design and Verilog HDL Fundamentals </title> <dc:identifier>ISBN:9781315218670</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1775075</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1315218674.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Joseph Cavanagh.<br /> Taylor and Francis 2008 9781315218670 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1775075">Place hold on <em>Digital Design and Verilog HDL Fundamentals</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1775075</guid> </item> <item> <title> Digital Design: With an Introduction to the Verilog HDL, VHDL, and System Verilog </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1678816</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Mano, M. Morris; Ciletti, Michael D. .<br /> Pearson 2026 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1678816">Place hold on <em>Digital Design: With an Introduction to the Verilog HDL, VHDL, and System Verilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1678816</guid> </item> <item> <title> Digital Integrated Circuit Design Using Verilog and SystemVerilog </title> <dc:identifier>ISBN:9780124080591</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1840992</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0124080596.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Mehler, Ronald.<br /> Elsevier 2014 9780124080591 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1840992">Place hold on <em>Digital Integrated Circuit Design Using Verilog and SystemVerilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1840992</guid> </item> <item> <title> Digital Systems Design Using Verilog </title> <dc:identifier>ISBN:9789391566272</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1490918</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/9391566278.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Lizy Kurian John.<br /> Cengage 2013 9789391566272 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1490918">Place hold on <em>Digital Systems Design Using Verilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1490918</guid> </item> <item> <title> Digital VLSI Design and Simulation with Verilog </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1719996</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Lata Tripathi.<br /> IEEE </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1719996">Place hold on <em>Digital VLSI Design and Simulation with Verilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1719996</guid> </item> <item> <title> Digital VLSI Design and Simulation with Verilog </title> <dc:identifier>ISBN:9781119778097</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1550982</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1119778093.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Suman Lata Tripathi.<br /> Wiley 2021 9781119778097 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1550982">Place hold on <em>Digital VLSI Design and Simulation with Verilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1550982</guid> </item> <item> <title> Introduction to logic circuits &amp; logic design with verilog </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=779644</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By LaMeres Brock J..<br /> Switzerland Springer 2019 .<br /> xvi,485p. cm..<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=779644">Place hold on <em>Introduction to logic circuits &amp; logic design with verilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=779644</guid> </item> <item> <title> Introduction to logic circuits &amp; logic design with verilog </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=779553</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By LaMeres Brock J..<br /> Switzerland Springer 2017 .<br /> xvi,459p. cm..<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=779553">Place hold on <em>Introduction to logic circuits &amp; logic design with verilog</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=779553</guid> </item> <item> <title> A Practical Guide to Verilog-A </title> <dc:identifier>ISBN:9781484263518</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1665985</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1484263510.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Slobodan Mijalkovi?.<br /> Springer 2022 9781484263518 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1665985">Place hold on <em>A Practical Guide to Verilog-A</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1665985</guid> </item> <item> <title> Principles of Verilog Digital Design </title> <dc:identifier>ISBN:9781003187196</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1741162</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1003187196.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Wen-Long Chin.<br /> Taylor and Francis 2022 9781003187196 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1741162">Place hold on <em>Principles of Verilog Digital Design</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1741162</guid> </item> <item> <title> Sequential Logic and Verilog HDL Fundamentals </title> <dc:identifier>ISBN:9781315214139</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1747071</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/131521413X.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Joseph Cavanagh.<br /> Taylor and Francis 2016 9781315214139 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1747071">Place hold on <em>Sequential Logic and Verilog HDL Fundamentals</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1747071</guid> </item> <item> <title> Verilog digital computer design Algorithms into hardware </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=790822</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Arnold Mark Gordon.<br /> New Jersey Prentice Hall 1999 .<br /> xxix,602p cm..<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=790822">Place hold on <em>Verilog digital computer design </em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=790822</guid> </item> <item> <title> Verilog HDL Digital design and modeling </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=784617</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Cavanagh Joseph.<br /> Boca Raton CRC Press 2012 .<br /> xviii;900p cm..<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=784617">Place hold on <em>Verilog HDL </em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=784617</guid> </item> <item> <title> Verilog HDL Digital design and modeling. </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=784348</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Cavanagh Joseph.<br /> Boca Raton CRC Press 2007 .<br /> xviii,900p cm..<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=784348">Place hold on <em>Verilog HDL </em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=784348</guid> </item> <item> <title> Verilog HDL Digital Design and Modeling </title> <dc:identifier>ISBN:9781315219547</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=1778296</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/1315219549.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Joseph Cavanagh.<br /> Taylor and Francis 2007 9781315219547 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=1778296">Place hold on <em>Verilog HDL</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=1778296</guid> </item> <item> <title> Verilog PLI handbook. </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=815360</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By Sutherland Stuart.<br /> 1999 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=815360">Place hold on <em>Verilog PLI handbook.</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=815360</guid> </item> </channel> </rss>
