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037 _aEBOOK
040 _aCRL
040 _beng
040 _cCRL
041 _2eng
041 _aeng
084 _qCRL
100 _aLata Tripathi
_91134593
245 0 _aDigital VLSI Design and Simulation with Verilog
260 _bIEEE
856 _uhttps://ieeexplore.ieee.org/servlet/opac?bknumber=10513526
942 _cEBOOK
999 _c1719996
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