| 000 | 00886nam a2200253Ia 4500 | ||
|---|---|---|---|
| 003 | OSt | ||
| 005 | 20220930093158.0 | ||
| 006 | a|||||r|||| 00| 0 | ||
| 007 | ta | ||
| 008 | 220926b |||||||| |||| 00| 0 eng d | ||
| 024 | _a29381 | ||
| 037 | _cTheses | ||
| 040 |
_aCRL _cCRL _beng |
||
| 041 |
_2eng _aeng |
||
| 100 |
_aSingh Kunwar Au. _9551009 |
||
| 110 | _aUniversity of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering | ||
| 245 | 0 | _aDesign and optimization of digital cmos integrated circuits for minimum power-delay-area product | |
| 260 | _c2015 | ||
| 300 |
_axxi,218p. _ap. _ccm. |
||
| 700 |
_a Gupta Maneesha Gu. _9551010 |
||
| 700 | _aUniversity of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering | ||
| 942 |
_cDIS _2CC |
||
| 999 |
_c884938 _d884938 |
||