VLSI test principles and architecture design for testability. (Record no. 789497)

MARC details
000 -LEADER
fixed length control field 00731nam a2200253Ia 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20220928131101.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 220927b |||||||| |||| 00| 0 eng d
037 ## - SOURCE OF ACQUISITION
Terms of availability Textual
040 ## - CATALOGING SOURCE
Original cataloging agency SDCL
Transcribing agency SDCL
Language of cataloging eng
041 ## - LANGUAGE CODE
Source of code eng
Language code of text/sound track or separate title eng
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Wang Laung-Terng Ed.
9 (RLIN) 477041
245 #0 - TITLE STATEMENT
Title VLSI test principles and architecture design for testability.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Amsterdam
Name of publisher, distributor, etc. Morgan Kaufmann
Date of publication, distribution, etc. 2006
300 ## - PHYSICAL DESCRIPTION
Extent xxiii,777p
Dimensions cm.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element VLSI
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Wu Cheng-Wen Ed.
9 (RLIN) 477042
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Classification part D651:81, P6
Koha item type Textual
Source of classification or shelving scheme Colon Classification (CC)
Holdings
Withdrawn status Lost status Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Barcode Date last seen Price effective from Koha item type
        South Campus Library South Campus Library 2022-09-28   D651:81 P6 SC1303272 2022-09-28 2022-09-28 Textual
Copyright @ Delhi University Library System