Design and optimization of digital cmos integrated circuits for minimum power-delay-area product
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TextLanguage: English Publication details: 2015Description: xxi,218p. p. cm
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Design and optimization of digital cmos integrated circuits for minimum power-delay-area product
APA
Singh Kunwar Au, University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering, Gupta Maneesha Gu & University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering. (2015). Design and optimization of digital cmos integrated circuits for minimum power-delay-area product. : .
Chicago
Singh Kunwar Au, University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering, Gupta Maneesha Gu and University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering. 2015. Design and optimization of digital cmos integrated circuits for minimum power-delay-area product. : .
Harvard
Singh Kunwar Au, University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering, Gupta Maneesha Gu and University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering. (2015). Design and optimization of digital cmos integrated circuits for minimum power-delay-area product. : .
MLA
Singh Kunwar Au, University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering, Gupta Maneesha Gu and University of Delhi. Faculty of Technology. Department of Electronics and Communication Engineering. Design and optimization of digital cmos integrated circuits for minimum power-delay-area product. : . 2015.